![]() For several years, Yu had been intrigued by Kohn’s zeal for building a superfast RISC microprocessor, but he felt Intel lacked the resources to invest in such a project. Yu, vice president and general manager of the company’s Component Technology and Development Group. ![]() The final decision rested with Albert Y.C. They were also already planning the more fully defined architecture, with memory management, cache, floating-point, and other features on the one chip, a versatility impossible with what they correctly assumed were the smaller transistor budgets of their competitors. The engineers knew their chip would not be the first in RISC architecture on the market, but the 64-bit technology meant that they would leapfrog their competitor’s 32-bit designs. The Intel team also speculated over what its competitors-such as MIPS Computer Systems Inc., Sun Micro Systems Inc., and Motorola Inc.-were up to. Minicomputer makers wanted speed, and confirmed the decision that RISC was the only way to go for high performance they also stressed the high throughput needed for database applications. Graphics workstation vendors, for their part, urged the Intel designers to balance integer performance with floating-point performance, and to make the chip able to produce three-dimensional graphics. Supercomputer makers wanted a floating-point unit able to process vectors and stressed avoiding a performance bottleneck, a need that led to the entire chip being designed in a 64-bit architecture made possible by the 1 million transistors. “We are all engineers,” Cornet told IEEE Spectrum, “so this is the type of need we are most familiar with: a computation-intensive, simulation-intensive system for computer-aided design.”ĭiscussions with potential customers in the supercomputer, graphics workstation, and minicomputer industries contributed new requirements for the chip. The chip, he predicted, would reach beyond the utilitarian line of microprocessors into equipment for the high-level engineering and scientific research communities. ![]() Jean-Claude Cornet, vice president and general manager of Intel’s Santa Clara Microcomputer Division, saw N10 as an opportunity to serve the high-performance microprocessor market. A later attempt was dropped when Intel decided not to invest in that particular process technology. One attempt went almost 18 months into development, but current silicon technology did not allow enough transistors on one chip to gain the desired performance. He had been hoping to get started on a RISC microprocessor design ever since joining Intel in 1982. Leslie Kohn, the project’s chief architect, had already earned the nickname of Mr. The paper was not to stay blank for long. But with the i860, then code-named the N10, the company planned a revolution.įreed from the limitations of compatibility with the 80X86 processor family, the secret N10 team started with nothing more than a virtually blank sheet of paper. The two chips have about the same area and use the same 1-micrometer CMOS technology then under development at the company’s systems production and manufacturing plant in Hillsboro, Ore. ![]() Now designated the i860, it entered development in 1986 about the same time as the 80486, the yet-to-be-introduced successor to Intel’s highly regarded 8026. But this long-deferred move into the booming market in reduced-instruction-set computing (RISC) was more of a shock, in part because it broke with Intel’s tradition of compatibility with earlier processors-and not least because after three well-guarded years in development the chip came as a complete surprise. The number of transistors alone marks a huge leap upward: Intel’s previous microprocessor, the 80386, has only 275,000 of them. 27, 1989, Intel Corp., Santa Clara, Calif., startled the world of high technology by presenting the first ever 1-million-transistor microprocessor, which was also the company’s first such chip to use a reduced instruction set. ![]()
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